1. Field of the Invention
The present invention relates in general to a data processing system and, in particular, to a data processing system including a superscalar processor. Still more particularly, the present invention relates in general to a superscalar processor and method for efficiently recovering from attempting to access misaligned data addresses.
2. Description of the Related Art
A superscalar data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per clock cycle, multiple independent functional units that can execute concurrently are required. These multiple instructions may be executed in their original sequence, or out of order in a sequence which is different in some way from the original sequence. Such a microprocessor architecture typically utilizes LOAD and STORE instructions to move data between storage locations such as main memory, cache, register locations, and/or other types of storage locations. A LOAD/STORE instruction includes an address of the data to be moved.
A microprocessor architecture defines a unit of memory addressability. The unit of memory addressability may be a single byte, two bytes, four bytes, or any other predetermined size. For example, if a four-byte addressable unit is utilized, four bytes of data will be considered to be a single address. Therefore, the possible addressable locations will be multiples of four bytes. The LOAD and STORE instructions will specify a particular starting point in the storage device. Four bytes of data will then be either loaded from or stored into the storage device starting at the defined starting point.
A problem arises when the data address may be a unit which is not divisible by the unit of the addressable units into which the memory is organized. For example, the memory may be organized in four-byte units while data may be addressed by an amount which has a non-zero remainder when divided by the natural word size. An instruction, such as a single LOAD/STORE instruction, may attempt to access data which is located across data boundaries. For example, a single LOAD instruction may attempt to load four bytes of data from a location starting in the middle of an addressable memory unit. In this case, the instruction may attempt to load data located in the last two bytes of one addressable unit and the two bytes of data located in the next consecutive addressable unit.
One known method for executing these types of instructions is to add hardware to the load/store unit and the data cache in the microprocessor making the load/store unit and data cache capable of executing misaligned instructions. The load/store unit is then capable of addressing the middle of an addressable unit and across a data boundary. This method adds complex hardware to the architecture which increases the cost of producing the processor. The required addition of a second read/write port in the data cache is prohibitively expensive in terms of area.
Another known method is to solve this problem in software so that no additional hardware is needed. Although this solution does not increase the cost as significantly as the hardware solutions, this solution tends to be very slow and requires that significant efforts are taken by programmers to minimize such occurrences.
Therefore a need exists for a data processing system and method for efficiently recovering from misalignment of data addresses.